`include "mod_a.v"
`include "mod_b.v"

`timescale 1ns/1ns

module TBAsync();

reg clk_100M;
reg clk_125M;
reg sys_rst_n;
wire req;
wire mod_a_captured;
wire backgot;

mod_a mod_a_u0 (
    .clk(clk_100M),
    .rst_n(sys_rst_n),

    .start_req(req),
    .captured(mod_a_captured)
);

mod_b mod_b_u0 (
    .clk(clk_125M),
    .rst_n(sys_rst_n),

    .emit_sig(req),
    .back_req(mod_a_captured),
    .backgot(backgot)
);

int cnt;

initial begin
    $display("Testing  start.");
    $dumpfile("tb_async.vcd");
    $dumpvars(0, TBAsync);

    sys_rst_n = 1'b0;
    #1 clk_100M = 0;
    #5 clk_125M = 0;
    
    #5 sys_rst_n = 1'b1;

end

always #4 clk_125M = ~clk_125M;
always #5 clk_100M = ~clk_100M;


always @(posedge clk_100M or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
        cnt <= 0;
    end else begin
        if (cnt < 1000)
            cnt <= cnt + 1;
        else
            $finish;
    end
end

endmodule
